The present invention relates to a semiconductor device and a manufacturing method of the same and, more particularly, to a technique effectively applied to the semiconductor device with a resistor element made of silicon.
Japanese Patent Laid-Open No. 2000-307060 discloses the technique in which a refractory metal silicide layer is formed as a resistive electrode on an upper surface of a poly-Si layer and an aluminum wiring is connected to the refractory metal silicide layer through a contact and, in this manner, a resistor element using a poly-Si layer is formed (see Patent document 1).
Japanese Patent Laid-Open No. 2000-31295 discloses the semiconductor integrated circuit device provided with: a transistor having an operation region and an electrode formed by processing a salicide layer; and a resistor element having a salicide layer formed only at the connection part thereof, wherein both the salicide layers are formed in the same process (see Patent document 2).
[Patent Document 1]
Japanese Patent Laid-Open No. 2000-307060
[Patent Document 2]
Japanese Patent Laid-Open No. 2000-31295